(a) Field of the Invention
The present invention relates to an interconnection in a semiconductor device and a method for forming the same, and more particularly to a dual damascene interconnection in a semiconductor device and a method for forming the same.
(b) Description of the Related Art
In fabricating a semiconductor device using a design rule of below 0.13 μm for high integration, a copper interconnection formed by dual damascene is being widely used. With the copper interconnection, a material having a low dielectric constant, such as a fluoro-silicate glass (FSG) film, is used as an intermetal insulating film. In this case, fluorine (F) contained in the FSG film may raise several problems, which will be described in detail with reference to the accompanying drawings below.
FIG. 1 is a sectional view illustrating a dual damascene interconnection in a conventional semiconductor device.
Referring to FIG. 1, an intermetal insulating film 130 including a FSG film 132 is formed on a lower metal interconnection film 110 composed of a copper film and disposed in a lower insulating film 100. The intermetal insulating film 130 includes a lower capping layer 131 and an upper capping layer 133, with the FSG film 132 interposed therebetween, each of which is composed of an undoped silicon glass (USG) film.
A via hole 141 penetrates through the intermetal insulating film 130 and an etch stop film 120 to expose the lower metal interconnection film 110, and a trench 142 having a width wider than that of the via hole 141 is formed on the via hole 141. A barrier metal layer 150 composed of a Ta/TaN film is formed on sidewalls of the via hole 141 and the trench 142 and on an exposed surface of the lower metal interconnection film 110. In addition, an upper metal interconnection film 160 with which the via hole 141 and the trench 142 are completely filled is formed on the barrier metal layer 150.
In the above-described dual damascene interconnection, the lower capping layer 131 and the upper capping layer 133 are formed in order to prevent the fluorine component of the FSG film 132 from diffusing to the upper and lower layers that sandwich the FSG file 132 therebetween. However, as recognized by the present inventor, the FSG film 132 and the barrier metal layer 150 directly contact each other on a sidewall of the FSG film 132, or sidewalls of the via hole 141 and the trench 142. Accordingly, there may arise a problem of adhesion between the FSG film 132 and the barrier metal layer 150. More specifically, when the concentration of fluorine (F) component is increased in order to further lower a dielectric constant, the adhesion between the FSG film 132 and the barrier metal layer 150 is deteriorated, which may result in a peeling phenomenon, thus lowering the reliability of the semiconductor device.
In addition, when the above described dual damascene interconnection is formed, the FSG film 132 may be exposed to the air through the via hole 141 and the trench 142. In this case, the fluorine (F) component contained in the FSG film 132 reacts with water in the air to thereby form SiOF on a surface of the lower metal interconnection film 110. SiOF creates an undesired silicon oxide film in a subsequent thermal process. In the presence of this silicon oxide film, when the barrier metal layer 150 is formed, a low electrical resistance contact between the barrier metal layer 150 and the lower metal interconnection film 110 may not be effectively made due to the presence of a native silicon oxide film.